1. Field of the Invention
The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a bottom package of a PoP (package-on-package) that accommodates an active or passive component.
2. Description of Related Art
Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages.
One limitation in reducing the size of a package (e.g., either the top package (the memory package) or the bottom package (the SoC package) in the PoP package) is the size of the substrate used in the package. Thin substrates and/or coreless substrates (e.g., laminate substrates) have been used to reduce the thickness of the packages to more desirable levels. The likelihood of warping, caused by the difference in thermal characteristics of materials, may increase, however, due to the use of thinner substrates in the package. Warping likelihood may increase because the thin or coreless substrates have less mechanical strength to resist the effects caused by differences in thermal characteristics between materials.
Thus, as PoP packages get thinner and pitch (e.g, spacing between contacts) gets finer, warping has an increased role in failure or reduced performance of the PoP package and/or problems in reliability of devices utilizing the PoP package. For example, the differences in warpage behavior between top and bottom packages in the PoP package may cause yield loss in the solder joints coupling the packages (e.g., either shorts or bridges between adjacent solder joints or open or disconnected opposing solder terminals depending on the warpage behavior). A large fraction of PoP structures may be thrown away (rejected) because of stringent warpage specifications placed on the top and/or bottom packages. Rejecting PoP structures contributes to low pre-stack yield, wasted materials, and increased manufacturing costs. Thus, many advancements and/or design modifications are being taken and contemplated to inhibit warping in packages using thin or coreless substrates and packages with fine ball pitches.
One solution that has been used for fine ball pitches has been the use of an encapsulant or molding material on the top surface of the bottom package. The encapsulant may be used to inhibit shorting between solder joints during solder reflow. The encapsulant may also provide electrical insulation between adjacent solder joints during use of the PoP package and/or provide mechanical support for the die (e.g., SOC) coupled to the bottom substrate. Through-mold vias (TMVs) are typically used to provide terminals on the bottom package to connect to terminals (e.g., solder balls) on the top package. One problem that arises with the use of TMVs is that during formation of the vias (typically done with laser ablation), the vias may be overablated. Overablation may create thin walls in the encapsulant between adjacent TMVs. These thin walls may allow solder to flow between adjacent TMVs during solder reflow and bridge (short) the corresponding adjacent solder joints. The use of TMVs may also lead to open defects in the PoP package. Open defects may be caused by shifting of the top package and/or bottom package, poor control of the TMV shape, and/or sticking of solder balls due to ball size. As PoP ball pitch gets smaller, problems caused by bridging or open defects may become more frequent and/or more severe.